1/8 september 2000 AN1268 application note an overview of the lpc flash interface contents n introduction n why a new interface? n what is the lpc protocol? n how does the fwh flash memory communicate on the lpc bus? C fwh read cycles C fwh write cycles C abort mechanism n a/a mux mode n conclusion introduction stmicroelectronics new m50fw040 firmware hub takes ad- vantage of a new motherboard intra-connect protocol known as the low pin count interface specification or lpc. the lpc bus is a high-speed interface between a motherboard chipset and onboard peripheral functions. the lpc bus is quickly becoming the replacement for the slower industry standard architecture (isa or x-bus) on motherboards for connection of super i/o, system management and, now, flash for the system bios. why a new interface? earlier pc systems contained an 8/16-bit expansion bus called the isa bus; the bios was connected to a subset of this bus, often referred to as the x-bus. this architecture provided flexi- bility for add-in card designers and system designers but the isa bus was slow and had interoperability problems due to lack of standardization of software and hardware. the pc mother- board with isa/x-bus architecture is shown in figure 1. figure 1. earlier pc architecture with isa/x-bus ai03439 sdram expansion slots i 2 c bus expansion slots >266 mbyte/s fsb 66-133mhz agp 2x pci 2.1 133mbyte/s ata/66 cpu north bridge south bridge flash super i/o ide 3d graphics audio modem usb screen serial parallel keyb'd mouse isa (8mhz) x-bus (isa)
AN1268 - application note 2/8 the lpc interface was defined as part of the evolution to a legacy-free and more user friendly pc archi- tecture. it also has higher bandwidth potential, operating at 33 mhz rather than the 8 mhz isa bus. since early 1998 there has been an industry wide push to eliminate the isa bus from pc systems in an effort to reduce the cost of service calls to system and operating system suppliers. several key industry partners defined this transition initially in the pc97 design guidelines. the follow-on specifications (pc99) have provided an even more detailed transition plan that endorses plug-and-play compliance as the pre- ferred expansion mechanism. in the same way that pci, usb, and p1394 interfaces have provided a mi- gration path away from isa bus expansion cards, the lpc bus provides a transition to eliminate isa motherboard devices. table 1 shows the migration history of the key motherboard subsystems and i/o interfaces. table 1. evolution of motherboard interconnect technology as shown in table 1, the peripheral i/o functions that previously connected via the isa bus have moved to plug-and-play structures such as pci and usb. as this migration occurred, the only remaining function attached to the isa bus was the flash memory containing the bios. lpc was invented as a better way to interconnect the core chipset and onboard peripheral functions. subsystem legacy non-legacy audio isa pci, ac97, usb expansion cards isa/eisa pci, usb network isa pci, usb graphics isa pci, agp, embedded modem isa pci, usb, ac97 hard disk ide eide, p1394 super i/o isa pci, lpc bios isa (x-bus) lpc
3/8 AN1268 - application note what is the lpc protocol? the lpc bus is a multiplexed bus running at 33 mhz synchronously with the pci bus. it uses pci driver technology on the i/o pins in order to sustain high throughput rates. low pin count refers to the fact that the interface only requires 7 to 13 signal pins, compared to 30 or more for the isa bus. the lpc bus was first introduced on intels 810 chipset in 1999. the lpc bus matches the low-latency hub interconnect better than the isa bus, resulting in better overall system performance. the lpc bus is capable of performing all the x-bus cycle types, including memory, i/o, dma, bus master, in addition to the fwh cycles that access the flash memory. fwh accesses utilize unique read/write lpc bus cycles to access the memory array, block locking, status, and gpi registers of the fwh flash memory. the lpc bus interface is synchronous; it uses pci clock protocol and signaling resulting in more controlled transfer rates and less conflicts with system resources. from a system point of view, overall performance can be better than isa bus systems because the busses are more balanced. there is less opportunity for high latency peripherals to slow performance of upstream busses. figure 2. new motherboard architecture with firmware hub ai03440 sdram cpu memory hub (mch) i/o controller hub (ich) firmware hub (fwh) flash memory super i/o ide screen serial parallel keyb'd mouse rdram rambus 1066 mbyte/s mth >1000 mbyte/s 1066 mbyte/s agp 4x 266 mbyte/s hub link 266 mbyte/s pci usb pov eeprom fan/temp sense audio codec modem codec i2c (smbus) ac'97 ata/66 future functions lpc (33mhz) spkr pots frame buffer 3d graphics
AN1268 - application note 4/8 how does the fwh flash memory communicate on the lpc bus? the lpc bus consists of 7 essential and 6 optional signals. the stmicroelectronics m50fw040 utilizes the 7 essential signals and does not use the 6 optional signals that are normally reserved for bus master- ing and dma functions. please refer to the m50fw040 data sheet for specification of the st firmware hub pin descriptions, including the non-lpc signals such as top block lock, reset and id select signals. table 2. low pin count interface signals the lpc bus uses a multiplexed protocol on the 4-bit lad0-lad3 bus to transfer command, address, and data information serially between the host and peripherals (m50fw040 fwh is considered a peripheral). a cycle is started on the rising edge of lclk when lframe is asserted and a valid cycle type is driven on lad0-lad3 by the host. the fwh flash memory uses lpc signals, but uses cycle types which are unique. valid cycle types for the fwh flash memory are 1101b (read) and 1110b (write). these are the only cycle types recognized by the m50fw040 and they are ignored by other motherboard peripherals. these unique cycle types have been designed specifically to avoid conflicts with other devices. all the other lpc cycle types are ignored by the fwh. lpc signal m50fw040 pin required description lad0-lad3 fwh0-fwh3 y multiplexed command/address/data bus lframe fwh4 y indicates the start of a new cycle or aborts a cycle lreset init y pci reset lclk clk y 33mhz pci clock optional lpc signals ldrq C n encoded dma request from peripheral serirq C n serialized irq request from peripheral clkrun C n dma/bus master pci clkrun signal pme C n power management event signal, pci pme lpcpd C n peripheral power down input lsmi C n peripheral smi output pin
5/8 AN1268 - application note fwh read cycles valid fwh read cycles are initiated by the i/o controller hub (ich) asserting 1101b on fwh0-fwh3 with fwh4 low. all data transfers are valid on the rising edge of each clock cycle. the fwh read waveforms are shown in figure 3, followed by a description of each clock cycle in table 3. figure 3. fwh read cycle waveforms table 3. fwh read cycle signal descriptions signal clock cycles fwh0- fwh3 peripheral i/o description start 1 1101b i on the rising edge of clk with fwh4 low, the contents of fwh0-fwh3 indicate the start of a fwh read cycle. idsel 1 xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. addr 7 xxxx i a 28-bit address phase is transferred starting with the most significant nibble first. msize 1 0000b i always 0000b (single byte transfer). tar 1 1111b i lpc host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. ta r 1 1111b (float) o the fwh flash memory takes control of fwh0-fwh3 during this cycle. wsync 2 0101b o the fwh flash memory drives fwh0-fwh3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. rsync 1 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating that data will be available during the next clock cycle. data 2 x x x x o data transfer is two clk cycles, starting with the least significant nibble. tar 1 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. ta r 1 1111b (float) n/a the fwh flash memory floats its outputs, the lpc host takes control of fwh0-fwh3. ai03437 clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize tar sync data tar 11712322
AN1268 - application note 6/8 fwh write cycles valid fwh write cycles are initiated by the i/o controller hub asserting 1110b on fwh0-fwh3 with fwh4 low. all data transfers are valid on the rising edge of each clock cycle. the fwh write waveforms are shown in figure 4, a description of each clock cycle is in table 4. figure 4. fwh write cycle waveforms table 4. fwh write cycle signal descriptions signal clock cycles fwh0- fwh3 peripheral i/o description start 1 1110b i on the rising edge of clk with fwh4 low, the contents of fwh0-fwh3 indicate the start of a fwh write cycle. idsel 1 xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. addr 7 xxxx i a 28-bit address phase is transferred starting with the most significant nibble first. msize 1 0000b i always 0000b (single byte transfer). data 2 x x x x i data transfer is two cycles, starting with the least significant nibble. tar 1 1111b i the lpc host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. ta r 1 1111b (float) o the fwh flash memory takes control of fwh0-fwh3 during this cycle. sync 1 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating it has received data or a command. tar 1 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b, indicating a turnaround cycle. ta r 1 1111b (float) n/a the fwh flash memory floats its outputs and the lpc host takes control of fwh0-fwh3. ai03441 clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize data tar sync tar 11712212
7/8 AN1268 - application note abort mechanism once valid start, idsel, and msize fields are received, the fwh flash memory will always assume that the following inputs are valid. in general, the fwh flash memory will not indicate that it has received an invalid field. if the fwh flash memory receives an invalid msize (i.e. not 0000b), the internal state machine that operates the lpc bus will reset and no operation will be attempted. the lpc bus provides an abort mechanism. whenever fwh4 is low, the fwh will tri-state its outputs and the lpc interface state machine will remain in reset state. using this protocol, the i/o controller hub can abort any cycle by holding fwh4 low for several cycles. note that the fwh flash memory internal operations are independent from the lpc bus interface. the internal fwh flash memory state machine will not begin a flash program or erase operation until it has received the last data nibble from the i/o controller hub. these features insure data integrity for the fwh flash memory during program and erase operations. a/a mux mode the m50fw040 firmware hub also provides an address/address mux mode (a/a mux) for out of system programming. this interface is enabled by a strapping option on an input pin. a/a mux mode is not intend- ed for normal (in-system) operation, rather it is used for bulk programming out of the system and during motherboard manufacturing. more information about a/a mux mode can be found in the m50fw040 data sheet. conclusion the lpc bus interface is ideal for interconnect between onboard peripheral devices. it is faster than the isa bus for all cycle types. it is more controlled because there are no unknown adapter cards that can cause resource conflicts. finally, the boot process is simplified by using this fundamental protocol. in ad- dition to flash, the lpc bus holds promise for even more peripheral content in future pc motherboard, mobile, and server platforms. the new stmicroelectronics m50fw040 firmware hub uses the lpc bus to achieve higher bandwidth potential, and reliable data integrity.
AN1268 - application note 8/8 if you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address: ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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